Double-patterning lithography (DPL) is a likely short-term solution for maintaining the current pace of scaling in integrated chip manufacturing. Specifically, DPL is one of the many resolution enhancement techniques (RET) that have been introduced to push the limit of optical lithography. DPL is a natural extension to the single-patterning lithography that uses two separate patterning processes to form two coarser patterns, which are combined to form a single finer pattern.
DPL can be implemented with different manufacturing processes including, but not limited to, litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and spacer double-patterning (SDP). In SDP, features are defined by a sidewall spacer making it more suitable for well-structured memory cells rather than random logic circuit layouts.
DPL suffers from at least three impediments. First, because DPL typically requires the use of two critical photomasks to pattern a single layer, DPL exhibits higher mask-costs when compared to processes employing standard single-patterning. Second, the additional processing steps needed for the second pattern result in reduced fabrication throughput. Lastly, DPL may result in a tight overlay budget because the overlay of the second to the first pattern translates directly into critical dimension (CD) variability.
Another technical problem is CD bimodality, which has serious implication on design including, but not limited to, a larger within-die CD/delay variation. CD and electrical parameters of transistors typically follow a normal distribution with some standard deviation and mean, which deviates slightly from the target. Since DPL has two separate exposure and etch steps, two populations exist: one for transistors formed by the first exposure/etch step and another for transistors formed by the second exposure/etch step.
In response to these shortcomings, attempts have been made to use DPL with a single photomask and, consequently, reduce cost. Such attempts typically consist of splitting a mask area into two regions, each corresponding to a different pattern (similar to a multi-layer reticle). In practice, this approach often results in a fabrication throughput even worse than that of standard-DPL and does not address the various other DPL technical challenges noted above.
Thus, it would be advantageous to employ a methodology that is compatible with standard DPL while mitigating or eliminating the various impediments discussed above.